1. Field of the Invention
This disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, this disclosure relates to a contact structure of a semiconductor memory device and a method of manufacturing the same.
2. Description of the Related Art
As semiconductor manufacturing technologies have been developed, semiconductor devices having high storage capacities have been widely employed in various electronic or electric apparatuses. Particularly, DRAM devices such as those containing single unit cells having one transistor and one capacitor have greatly improved in cell density. As cell density has increased, contact holes for connecting an upper conductive layer to a lower conductive layer have become smaller, whereas interlay insulating layers between the conductive layers have become thicker. Since the contact hole has a high aspect ratio (a ratio of a height of the contact hole respect to a width thereof), the process margin of a photolithography process for forming the contact hole has been reduced so that a minute contact hole may not be formed using a conventional semiconductor manufacturing technique. The solution has been to include landing pads in a DRAM device to reduce the aspect ratio of contact holes. Additionally, a self-aligned contact (SAC) structure was developed to form minute contacts in semiconductor devices having minute patterns of below about 0.1 μm, without failure of the semiconductor devices.
For example, Korean Patent No. 200,697 discloses a method of manufacturing a semiconductor device without a failure of a metal contact. According to the method, a guard ring is formed at the peripheral portion of a bit line to prevent the failure of the metal contact relative to the bit line.
In addition, U.S. Pat. No. 6,451,651 discloses a method of manufacturing a semiconductor device in which a metal contact is connected to a landing pad in a peripheral/core area of a semiconductor substrate by a self-alignment process.
FIGS. 1A to 1F are cross-sectional views illustrating a conventional method of manufacturing a semiconductor device in accordance with the above-mentioned U.S. Patent. In FIGS. 1A to 1F, ‘P’ indicates a peripheral/core area of the semiconductor device, and ‘C’ represents a cell area of the semiconductor device.
Referring to FIGS. 1A and 1B, after a gate insulation layer is formed on a semiconductor substrate 10 having an isolation layer thereon, a polysilicon layer, a metal silicide layer and a gate capping layer are successively formed on the gate insulation layer.
The gate capping layer, the metal silicide layer and the polysilicon layer are sequentially etched by a photolithography process to thereby form gate patterns 15 on the semiconductor substrate 10. After spacers are formed on sidewalls of the gate patterns 15, impurities are implanted at portions of the substrate 10 between the gate patterns 15 to form source/drain regions. As a result, transistors including the gate patterns 15 and the source/drain regions are formed on the substrate 10.
A silicon oxide layer is formed on the substrate 10 having the transistors thereon, and then the silicon oxide layer is planarized to form a first interlayer insulating layer 20 on the transistors and on the substrate 10. The first interlayer insulating layer 20 is etched to form contact holes that expose the portions of the substrate 10 between the gate patterns 15 in the cell area C.
After a conductive layer of polysilicon is formed on the first interlayer insulating layer 20 to fill the contact holes, the conductive layer and the first interlayer insulating layer 20 are partially etched to form a bit line contact pad 25 and a storage node contact pad 30 on the substrate 10. A second interlayer insulating layer 35 is formed on the contact pads 25 and 30 and on the first interlayer insulating layer 20, and then a first etch stop layer 40 is formed on the second interlayer insulating layer 35.
The first etch stop layer 40 and the second interlayer insulating layer 35 are etched to form a bit line contact hole exposing the bit line contact pad 25 in the cell area C. Here, the contact holes exposing portions of the substrate 10, which correspond to a bit line contact part and a metal contact part, are formed in the peripheral/core area P.
A metal barrier layer 45 is formed in the bit line contact hole of the cell area C and in the contact holes of the peripheral/core area P. After a metal layer is formed to fill the bit line contact hole of the cell area C and the contact holes of the peripheral/core area P, the metal layer is etched by a chemical mechanical polishing (CMP) process so that a bit line contact plug 50 is formed in the bit line contact hole of the cell area C, and metal contact pads 55 are formed in the contact holes of the peripheral/core area P, respectively.
Portions of the first etch stop layer 40 are removed except for a portion of the first etch stop layer 40 positioned adjacent to the metal contact pads 55 in the peripheral/core area P. After a nitride layer 60 and a bit line conductive layer 65 are formed on the whole surface of the substrate 10, the nitride layer 60 and the bit line conductive layer 65 are etched to form bit line patterns on the second interlayer insulating layer 35. Here, after a subsidiary oxide layer 70 and a sacrificial layer 75 are formed on the bit line conductive layer 65, the sacrificial layer 75, the subsidiary oxide layer 70, the bit line conductive layer 65 and the nitride layer 60 are successively etched by a photolithography process to thereby form the bit line patterns on the second interlayer insulating layer 35.
After forming a third interlayer insulating layer 80 on the bit line patterns, the third interlayer insulating layer 80 is planarized until the sacrificial layer 75 is exposed. In the peripheral/core area P, a bit line pattern connected to the bit line contact plug 50 has a relatively narrow width, whereas a bit line pattern connected to a metal contact plug has a relatively wide width.
Referring to FIG. 1C, the sacrificial layer 75 and the subsidiary oxide layer 70 on the bit line patterns are selectively etched to expose the bit line conductive layer 65. Hence, grooves 85 exposing the bit line patterns are formed on the third insulating layer 80.
Referring to FIG. 1D, after a nitride layer is formed on the third interlayer insulating layer 80 to fill the grooves 85, the nitride layer is etched to form nitride layer patterns 90 that fill the grooves 80. Here, a spacer 95 is formed on a sidewall of the groove 85 exposing the bit line pattern of the relatively wide width in the peripheral/core area P.
An additional oxide layer 100 and a second etch stop layer 105 are successively formed on the bit line pattern of the relatively wide width, on the nitride layer pattern 90, on the spacer 95 and on the third interlayer insulating layer 80.
The second etch stop layer 105, the additional oxide layer 100, the third interlayer insulating layer 80 and the second interlayer insulating layer 35 are partially etched in the cell area C, thereby forming a storage node contact hole that exposes the storage node contact pad 30. A conductive material is filled in the storage node contact hole to form a storage node contact plug 110 in the storage node contact hole.
Referring to FIG. 1E, after forming a storage node 115 connected to the storage node contact plug 110 using a mold oxide layer, a dielectric layer 120 and a plate electrode 125 are successively formed on the storage node 115 to complete a capacitor in the cell area C.
After completing the capacitor in the cell area C, the second etch stop layer 105 on the peripheral/core area P is removed. Then, a fourth interlayer insulating layer 130 is formed over the substrate 10 including the cell area C and the peripheral/core area P.
Referring to FIG. 1F, the fourth interlayer insulating layer 130 and the third interlayer insulating layer 80 are etched to form contact holes exposing the plate electrode 125, the metal contact pad 55 and the bit line patterns. When a conductive material is filled in the contact holes, metal contact plugs 135, 140 and 145 are formed in the contact holes, respectively. The metal contact plugs 135, 140 and 145 connect upper wirings to the underlying conductive structures.
In the above-described method of forming a semiconductor device, it is desirable to increase the thickness of the nitride patterns to ensure a high process margin for forming the bit line patterns. However, increasing the thickness of the nitride patterns also excessively increases the thickness of the bit lines. Since intervals between the bit lines are very small in the semiconductor device having a design rule of below about 0.1 μm, the aspect ratios of the bit lines are thus greatly increased. As a result, the bit lines may be electrically shorted. In addition, because several additional layers are formed on the bit line patterns so as to form the metal contact plugs by the self-alignment process, the semiconductor manufacturing process is more complicated. Furthermore, the underlying conductive structures may be damaged because several etching s are performed to form the metal contact plugs.
Meanwhile, since the size of the landing pad in the peripheral/core area has been reduced because DRAM devices are high density, an overlap margin for forming a metal contact relative to the landing pad is also greatly decreased. Although the design rule of the peripheral/core area may be increased to overcome this problem, there is a tradeoff in that throughput of the DRAM device manufacturing process may be reduced.